1. Field of Use
The present invention relates to field of electronic testing and, in particular, to the testing of printed circuit boards (PCBs) and to writable memory devices, volatile or non-volatile, and other devices that may be mounted thereon. The invention more particularly relates to testing for proper connections to other parts of the PCB, testing for and accessing device identification data contained within the devices and for controlling built-in self test (BIST) and self-repair of those devices.
2. Related Art
The benefits of being able to test for proper connection between the various devices mounted on PCBs has long been recognized as beneficial both in fault detection and diagnosis. That is, while testing the PCB as a functional unit is important in itself, there are advantages to separately testing the interconnects, especially in PCB designs in which the functionality is complex. Such designs are sometimes referred to as being comprised of random logic, because the challenge of testing differs from that of more straightforward designs, such as is the case with, for example, main memory units. In the latter type, the same or similar clusters of logical functions may exist in, perhaps, over a hundred instances. Additionally, these clusters of logical functions may be the same or similar to those functions which have existed in digital computers for decades and for which tests have been developed and perfected over time.
Various methods have been developed to address the testing challenges of interconnect testing. One such method is termed “boundary scan,” where a secondary layer of logic (test logic) is added to the primary layer of logic (functional logic) of each boundary scan device and controlled by extra connections to the device. IEEE Standard 1149.1 defines a method of boundary scan widely used in the industry. IEEE Standard 1149.1 was developed as a refinement of an international industry effort termed “Joint Test Action Group” (JTAG). Presently, the term JTAG is also used to refer both to devices which are IEEE Standard 1149.1 compliant and devices which may not be in strict compliance to the standard. The term IEEE 1149.1 will be used herein to include both classes of devices (i.e., strictly compliant and not strictly compliant).
IEEE 1149.1 devices incorporate three or four extra test input connections (TDI, TCK, TMS or TDI, TCK, TMS, TRST*, respectively) to control the internal device test logic. Such a device operates in either a functional mode or a test mode, depending on the signals received at those test input connections and upon the time interval since the device was powered up. That is, it is a norm that IEEE 1149.1 devices with only the three extra test inputs are designed to achieve a completely functional (non-test) state within a given interval after power up. It should be noted that the term “state of a device” is used herein to refer to which logical layer is controlling the non-IEEE 1149.1 outputs of the device. That is, in the test state, the boundary scan layer controls most device outputs, whereas in the functional device state, the functional logic layer controls most device outputs. An exception is the single IEEE 1149.1 output connection (TDO), which is always controlled by the test logic. Most non-IEEE 1149.1 input connections are usually connected to the test logic for level sensing. Exceptions may be power and high-speed clock inputs. The extra IEEE 1149.1 connections (TDO, TDI, TCK, TMS and optional TRST*) are termed a “Test Access Port.”
While the IEEE 1149.1 capability has been included on many complex devices, such as microprocessors and the like, many simple devices, such as separate groups of AND or OR gates, for example, are not available in IEEE 1149.1 versions. In the case of such simple devices, the added IEEE 1149.1 logic might be more complex than the functional logic of the device. Also, the simple logic paths that these devices provide between more complex devices are often easily testable by means of the IEEE 1149.1 circuitry extant in those complex devices and automatic test pattern generation (ATPG) software commonly used to write IEEE 1149.1 test patterns. The decision not to include IEEE 1149.1 logic in a device is made by the device manufacturer, as a marketing choice. That is, for example, the manufacturer decides whether or not the additional cost of an IEEE 1149.1 version of a device will be sufficiently welcomed in the market.
Memory devices have largely fallen into the category of devices which do not incorporate IEEE 1149.1 circuitry. Reasons for manufacturer decisions not to include IEEE 1149.1 may be the extremely competitive nature of the memory device industry, the inherent propagation delay, however minor, of adding any circuitry to the functional connections and the PCB etch routing problems imposed by the IEEE 1149.1 interconnects. There may be other reasons, as well, including what may possibly be the main reason manufacturers do not include IEEE 1149.1 circuitry on most memory devices: the nature of PCB designs incorporating one or more clusters of those devices. A main memory PCB of a computer is an example of a cluster of memory devices. In some key respects, the designs of clusters of memory devices are very similar to those of the past and can be tested by test programs very similar to those developed over decades. These test programs generally have high fault detection and fault diagnosis capabilities. Hence, there is less overall economic advantage to be gained by adding IEEE 1149.1 circuitry to memory devices in comparison to adding it to microprocessors, for example, by the device manufacturer.
In memory device applications other than clustered applications, interconnect testing is often extremely difficult. That is, unless the memory device contains IEEE 1149.1 circuitry, its connection to one or more devices which do may not solve the test problem. For example, in a case where the memory device operation has timing requirements which cannot be met by boundary scan operations, such testing may be impossible. To address such problems, another standard has been proposed, IEEE Standard P1581 (hereinafter referred to as IEEE P1581). As with IEEE 1149.1, an IEEE P1581 device would have both a test mode and a functional mode. However, the circuitry used in the IEEE P1581 test mode would be much less complex than the circuitry required for IEEE 1149.1. The circuitry may be simple gates such as AND, NAND, OR, NOR, XOR and XNOR, connected between device inputs and outputs in predetermined patterns, although more complex logic functions, such as storage elements, are not precluded from use. These logic functions enable signals from IEEE 1149.1 circuitry in another device or devices to propagate through the memory device and stimulate inputs of the same or other IEEE 1149.1 devices. The use of simple gating in IEEE P1581 means there is a minimum of extra circuitry involved in the memory devices, although the economy of circuitry has little apparent relative effect on the cost of device fabrication because of the small size of either type of test circuit (i.e., IEEE 1149.1 vs. IEEE P1581) in comparison to the functional circuitry of a memory of substantial size. The principal benefit of IEEE P1581 as originally proposed, absent the benefit of the invention of the cross referenced related application, is that only one extra connection to the device is needed to select test mode or functional mode. In certain memory devices, there may even be one or more combinations of control input signals which serve no functional purpose. In such instances, one or more such control input signal combinations may be used to set or reset the test mode, obviating extra connections. Memory devices having such unused control input signal combinations, however, are the exception rather than the rule. Therefore, incorporating the originally proposed IEEE P1581 capability into a device will commonly require an otherwise unnecessary connection to the device. Even this single added connection will sometimes be considered by suppliers as presenting a marketing disadvantage in main memory applications, which represents the largest market for many memory devices and where, as stated, the test advantage of IEEE P1581 is somewhat diminished because of the availability of adequate test methods which work well without the IEEE P1581 test circuitry.
The ability to externally access and read the contents of a read-only register within a device which is programmed during device manufacture with a thereafter unalterable code is also considered very beneficial. When included in the device, this capability may represent the only means by which important variations in the basic design of a device may be detected in a practical way during test operations once the device manufacturing process is complete and, to an even greater extent, when the device has been connected to other devices on a PCB. An example of such a register is the 32-bit Device Identification Register included in IEEE 1149.1 devices, although non-IEEE 1149.1 identification schemes involving lesser or greater numbers of bits may be used to advantage.
The benefits of BIST and self-repair have also long been recognized. BIST may be conveniently controlled by means of the IEEE 1149.1 test access port. Self-repair, a method whereby extra sections of a device may be substituted for sections determined to be faulty, either automatically or via external commands, also may utilize the IEEE 1149.1 test access port for convenience. That is, a degree of inconvenience results when BIST and self-repair are controlled by other means. This is usually because extra connections to the device are required, along with other hardware external to the device.
The invention described in the inventor's related patent application, application Ser. No. 11/222,474 filed Sep. 7, 2005, allows operating mode control of volatile memory devices which, by their nature, need have no functional purpose between the application of power and the time data is first written into them. In devices designed according to that invention, test mode begins at power up and ends at the beginning of the first write. That invention does not include a provision for device identification, BIST and self-repair and is of minimal value in non-volatile writable memory applications, where data written prior to the previous power down may need to be accessed before the first write after the current powering up. Also, the inventor's referenced related patent application r may be impractical for use with test equipment having certain pattern application and/or test flow constraints. Additionally, the inventor's referenced related patent application has no provision to return to test mode once functional mode has been invoked without powering the memory device down and then up, an operation which may be impractical, for example, because of additional hardware requirements to do so without cycling power to the entire PCB, or because of additional requirements of either or both of the PCB hardware or test software if the entire PCB is to be powered down and then up.
Since filing the referenced related patent application, the inventor of the present invention has developed a number of methods of test mode entry and exit which, like the related patent application, require no extra device connections. The present invention is best understood when explained in light of these developments, thus, the term “present invention and related test mode control apparatus and methods” is used herein to refer to both the present invention and the stated developments without confusing matter to be claimed as part of the present invention from that which is not. It should be noted that one of the developments includes a means allowing a device designed according to the teachings of the related patent application to return to test mode once functional mode has been invoked. It should further be noted that the related test mode control methods are detailed in the three cross-referenced provisional applications and cross referenced disclosure document, with a single exception (the use of non-logic analog levels, stated previously herein).
Therefore, it is an objective of the present invention to provide a method of controlling a plurality of test operations without the need of extra device connections in an electronic device in which a test mode has already been established.
It is a further objective of the present invention to provide test operation control usable with IEEE P1581 devices which include device identification, BIST and self-repair operations in any combination in addition to IEEE P1581 continuity test operations.
It is a still further objective of the present invention that it be compatible with test equipment having certain pattern or test flow constraints.
It is an even still further objective of the present invention that it permit external access to an internal device register similar to the Device Identification Register of IEEE 1149.1 devices, examination of the contents of which allows practical differentiation between minor variations of the same basic device design, to the extent permitted by register programming during device manufacture.
The description of the IEEE P1581 Proposal, given above, taken with the sections titled “P1581 Concept” and “P1581 Test Gates” beginning on page 2 of the White Paper of the IEEE P1581 Working Group dated Jan. 3, 2007, previously incorporated herein, will hereinafter be termed “Proposed IEEE P1581 Architecture.”
The term “digital functional” in describing inputs and outputs may be used hereafter to refer to those device connections which specifically exclude dedicated test connections, power connections and analog connections, including high speed clocks. It is noted that “digital functional” connections referred to herein are sometimes referred to as “system” connections in other documents, such as IEEE Std. 1149.1.